Cadence

Full briefing

Cadence Design Systems, Inc. (NASDAQ: CDNS) is headquartered in San Jose, California, and is one of the two dominant EDA (Electronic Design Automation) software companies alongside Synopsys. Founded in 1988 through the merger of SDA Systems and ECAD, Inc., Cadence provides the software tools without which modern chip design is impossible at advanced nodes. EDA software is the invisible foundation of the semiconductor supply chain. Before a chip can be fabricated at TSMC or Samsung, it must be designed using EDA tools that perform: (1) RTL synthesis — translating hardware description language (Verilog/VHDL) into gate-level netlists; (2) Place and route — determining where each transistor, wire, and standard cell goes on the die; (3) Timing analysis — verifying that signals propagate correctly at the target clock speed; (4) Physical verification — checking design rules against the foundry's process design kit (PDK). Cadence's flagship tools include Virtuoso (analog and mixed-signal design, essential for RF and high-speed I/O), Genus/Innovus (digital synthesis and place-and-route), and Tempus (static timing analysis). These are licensed per seat, per year, making Cadence's revenue model recurring and relatively recession-resistant. At advanced nodes (below 5nm), EDA tools must model quantum effects, IR drop, electromigration, and multi-patterning — all requiring continuous R&D investment. Cadence co-develops process design kits (PDKs) with TSMC for each new process node, creating deep integration that makes switching EDA vendors mid-project extremely costly. Export control significance: In October 2022, BIS classified advanced EDA tools as export-controlled items requiring licenses for supply to certain Chinese entities. Cadence and Synopsys were specifically named as companies affected by the new ECCRN (Export Control Classification Number) additions. This restriction targets China's ability to design advanced chips domestically — without EDA tools, even if China acquires fab equipment, its engineers cannot design sub-7nm chips.